1. Field of the Invention
The present invention relates to nanodevices and methods for making them and, more particularly, to nanodevices having superlattice structures and methods for making such devices.
2. Related Art
Nanotechnology is any technology which exploits phenomena and structures that occur at the nanometer scale, which is usually 0.1˜100 nanometers. Generally, nanomaterials involved in nanotechnology can be defined as those have nanostructured components at the nanometer scale. For example, nanomaterials with one dimension in the nanoscale are known as two-dimensional nanomaterials, such as thin films or surface coatings having a thickness at nanometer scale; nanomaterials with two dimensions in the nanoscale are known as one-dimensional nanomaterials, such as nanowires and nanotubes; and nanomaterials with three dimensions in the nanoscale are known as zero-dimensional nanomaterials, such as particles or quantum dots. Due to two principal factors, i.e., increased relative surface area and quantum effects, nanomaterials exhibits significantly different properties from other materials. For example, nanomaterials may have high Young's modulus, increased energy gap, and single electron effects.
It is known in the art that superlattice structures, i.e., composite structures made of alternating ultrathin layers of different component materials, can be made on the nano-scale and have potential applications in such areas, for example, as optoelectronic devices, optical sensors, semiconductors, and thermoelectric transformation. Generally, such superlattice structures are mainly composed of III-V group (such as GaAs/AlGaAs), II-VI group (such as ZnSe/ZnCdSe), and/or IV-IV group (such as Si/GeSi) semiconductor materials. Methods for synthesis of the superlattice structures have mainly included molecular beam epitaxy and chemical vapor deposition.
With the development of nanotechnology, superlattice structure was applied in one-dimensional nanomaterials for extending their functions. For example, Si/GeSi superlattice nanowires, GaAs/GaP superlattice nanowires, InP/InAs superlattice nanowires, and ZnO/InZnO superlattice nanowires have been reported in recent years. These semiconductor superlattice nanowires are all synthesized by vapor-liquid-solid (VLS) method, using gold (Au) or platinum (Pt) particles as the catalyst. The resulting nanowires are composed of different types of superlattice structures alternately stacked in series.
However, the VLS method for synthesizing superlattice nanowires has the following disadvantages:
First, in order to form a hetero-junction and a superlattice, the semiconductor materials must be compatible with the catalyst particles to form an alloy or solid solution at a high temperature. However, some valuable/useful materials do not alloy with gold or platinum. Therefore, possible candidates for the semiconductor material are limited, in that those materials incompatible with the catalyst cannot be applied to the superlattice nanowires.
Second, the VLS method for synthesizing the series-type superlattice nanowires is not compatible with the existing methods for synthesizing superlattice structures. In addition, the height of each of the superlattice structures must be precisely controlled during the VLS method. This need for precise control makes the VLS method difficult to implement.
Third, in order to construct a functional nanodevice, additional processes are needed for assembling and/or integrating the superlattice nanowires with a silicon substrate. The processes may include, e.g., addressing, manipulating, and/or integrating the nanowires. However, the techniques for these processes is premature and/or developmental.
Accordingly, what is needed is a superlattice-based nanodevice structure having a desired function and a method for manufacturing such a nanodevice.